Virtual computer systems having a virtual computer implemented within a physical computer setup have been gaining widespread acceptance. In this connection, it is possible within the physical environment of a multi-processor system having numerous physical computers to provide virtual computers. Such virtual computers of multi-processor systems exist by utilizing logically partitioned resources. In other words, a plurality of physical computers making up the multi-processor system are logically partitioned and are shared by a plurality of virtual computers.
One such example of the prior art means for implementing such virtual computers is disclosed in Japanese Patent Laid-Open No. Hei 6-103092. The disclosure involves assigning all resources that were allocated to a first virtual computer, to a second virtual computer dynamically and collectively without initializing the first virtual computer again.
In the single or multiple processor setup wherein each processor has a TLB, it becomes necessary to erase specific entries from that TLB. An example of conventional techniques for erasing specific entries of a TLB is the use of an IPTE instruction as explained in "Instructions for the HITAC M Series Processors (M/ASA)" (8080-2-146, p. 253) issued by Hitachi, Ltd.
The IPTE instruction is used to erase TLB entries applicable to specific conditions. In a tightly-coupled multi-processor environment, the IPTE instruction erases the TLB entries that meet specific conditions in all data processors making up the multi-processor structure.
FIG. 4 is a flowchart of steps depicting how the IPTE instruction is conventionally executed by each of a plurality of data processors in a multi-processor system. The multi-processor setup of FIG. 4 comprises a large number of instruction processors IP0 through IPn (each referred to as an IP) and a control unit (referred to as a CU). In the example shown in FIG. 4, the IP0 is shown executing the IPTE instruction. The flow of the processing involved is described below.
(1) In carrying out the IPTE instruction, the IP0 first issues a RESERVE request to the CU preparatory to performing PTLB processing (called XPTLB hereinafter) on the other IP's (i.e., IP1 through IPn). The RESERVE request is a request for priority to avoid contention with the other IP's issuing XPTLB requests (step 201).
(2) Upon receipt of the RESERVE request, the CU checks to see if it is possible to issue an XPTLB request to the other IP's, i.e., if the other IP's are in XPTLB processing or are issuing any RESERVE request to the CU preparatory to XPTLB processing. The result is reported to the IP0 (steps 202 and 203).
(3) If the processing of the RESERVE request from the IP0 is found to be possible, the CU issues an XPTLB REQ (step 204) to all other IP's (IP1 through IPn in the example of FIG. 4).
(4) The IP1 through the IPn are currently executing their assigned tasks. Upon receipt of the XPTLB REQ from the CU, the IP's stop their ongoing task processing and start XPTLB processing. At the same time, the IP's send an XPTLB START report to the CU telling the latter that the XPTLB processing has started (steps 205, 207, 206 and 208).
(5) On receiving the XPTLB START report from all IP's, the CU sends an ALL XPTLB START report to the IP0, which originated the XPTLB REQ, telling the latter that the XPTLB processing has been started by all IP's (step 209).
(6) Meanwhile, after issuing the RESERVE request to the CU, the IP0 waits for a report from the CU. If the attempt to reserve has failed, the IP0 returns to step 101 and issues another RESERVE request to the CU. If the reserve attempt is successful, the IP0 waits for an ALL XPTLB START request from the CU. When the request is received, the IP0 executes its own PTLB processing. At the end of the PTLB processing, the IP0 sends a PTLB END report to the CU and terminates the processing (steps 210 through 212).
(7) Upon receipt of the PTLB END report from the IP0, the CU sends to all other IP's a PTLB END report indicating that the PTLB processing by the IP0, the originator of the XPTLB REQ, has ended, and terminates the processing (step 213).
(8) The IPTE instruction is an instruction that inhibits the reference to any TLB entry area by any other IP except the IP that issued the instruction, the inhibition lasting until the latter IP terminates its processing. Thus the IP1 through IPn wait in a loop for a PTLB END report from the CU. When the PTLB END report is received, the IP's resume processing of their tasks (steps 214 and 215).